Reg_block = my_reg_block::type_id::create("basic_block") Make sure you include your register model files in the testbench: `include "my_reg_file.sv"Ĭreate an instance of your register model in the initial-task: initial begin How to export your register model using the demo testbench Running the above command will generate an xml file under /path/to/uvm_reg_to_ipxact/scripts/xml/. IEEE 1685, “Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows,” describes an XML Schema for meta-data documenting Intellectual Property (IP) used in the development, implementation and verification of electronic systems and an Application Programming Interface (API) to provide tool access to the meta-data. Here is a thorough presentation for the UVM_REG model. UVM_REG is an abstract SystemVerilog model for registers and memories from the DUT. The application is available for free under the Apache License 2 and it can be downloaded from GitHub uvm_reg_to_ipxact repository. You can use this application to generate IP-XACT models from existing UVM register models in order to ease IP-XACT adoption. This post presents a simple application for exporting existing UVM/SystemVerilog register models to an IP-XACT file.
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